In many applications, digital data must be compared against programmable lower and upper numeric values. For example, a computer may utilize a virtual memory in which a selectable contiguous part of the virtual memory is mapped into random access memory (RAM) providing relatively faster read/write access times. Most of the instructions executed on the computer address locations within the fast RAM, however certain relatively-infrequent instructions such as load and store may address any location within the virtual memory. Hence apparatus is needed which can operate in real time to detect numeric values, here addresses, which fall outside a pair of numeric boundaries.
The prior art has constructed such bounds checker apparatus with discrete medium-scale integrated circuit (MSI) devices; in one instance, a 16-bit checker consisting of four 8-bit registers and four 8-bit comparators. This approach is undesirable for a variety of reasons; foremost among them are the cost of the individual components over that of a single-chip component and the large board area consumed by a number of individual components.
Other desirable features of the prior art discrete component approach are high power consumption, fabrication costs of interconnecting the terminal plus of the individual components, the inter-component propagation delays and the inherent lower reliability of a multi-chip implementation as compared with a single-chip version.
In addition, the use of individual components made each application of a bounds checker a custom designed project with the attendant design costs and debugging requirements.